Direct gate-controlled NDR characteristics in surface tunnel transistor

Abstract

Tunneling devices have attracted much interest because of their increased functionality due to NDR characteristics and inherently high-speed switching characteristics. Various tunnel transistors based on resonant tunneling have been studied up to now. Recently, we proposed a new tunnel device, the surface tunnel transistor (STT)'-'), in which an interband tunneling current between a degenerate n+-channel and p'-drain is controlled by a gate voltage. In order to implement the STT, we have developed a new fabrication process 'utilizing MBE regrowth techniques and observed the direct modulation of NDR characteristics by the gate in the new structure. Moreover, utilizing these NDR characteristics of the STT, a bistable circuit consisting of only two components (one STT and one load resistor) was realized and its operation was successfully confirmed. An STT with a VMOS-like structure was fabricated using a GaAdAlGaAs heterostructure. A 500-nm n+-GaAs source (n=lxlO" cm-'), a 200-nm i-GaAs layer, and a 150-nm p+-GaAs drain (p=1x1020 ~ m ~ ) were successively grown by MBE at 520 "C. In this device, it is important that the drain region should be highly degenerate and have a sharp doping interface with the i region. After making a sloped mesa structure by wet-chemical etching down to the source layer, the surface was cleaned at 410 "C using hydrogen radicals generated by cracking with a W-filament to regrow a channel and a gate layer, Since the residual oxygen at the regrown interface causes an increase of the valley current which weakens the NDR characteristics, it is important that the residual oxygen concentration be made as low as possible. Next, a 12-nm n+-GaAs channel (n=lxlO" cm"), a 40-nm i-Ab,Ga,7As gate insulator and a 10-nm p+-GaAs gate electrode (p=7x1Ol9 ~ m ~ ) were regrown by MBE at 520 "C. An interband tunneling junction is formed between the n+-channel and the p+-drain. After delimiting the gate region, the source, gate and drain electrodes were formed using lift-off techniques. The drain current of the fabricated STT exhibits clear NDR characteristics at room temperature under forward drain-bias condition. When the gate voltage changes from -0.8 V to 0.8 V, the peak-to-valley current ratio (PVR) increases from 1.25 to 4.80 and the peak current increases from 0.029 to 0.32 pA/pm. This increase of both PVR and peak current density with increasing the gate voltage reflects the direct modulation of the tunneling junction by the gate. In order to demonstrate the functionality of the STT, a bistable circuit was implemented consisting of only one STT and a 21-WZ load resistor connected to the drain in series. Bistable operation with output drain voltages of V,=0.25 V and Vp0.35 V was obtained at VG=0.4 V. Since the NDR characteristics can be controlled by the gate voltage, switching between these output levels can be performed by applying a voltage pulse to the gate, When the positive (negative) pulse of 0.2 V is applied to the gate, the drain output level become low (high) and its level was hold after the pulse elimination. Thus, the bistable operation was confirmed. Since the STT benefits from the increased functionality due to NDR characteristics and the normal operation capability with the gate length reduced down to the tunneling barrier width (-10nm), the STT has an advantage for device-size reduction and high level integration, and is expected as the key device in future sub-0.1 pm ULSI circuits.