High-voltage NMOS in 0.5 /spl mu/m CMOS technology for fast switching applications

Abstract

This paper describes high-voltage NMOS devices implementation in a deep submicron 0.5 /spl mu/m CMOS process, only resorting to design layout strategies. Experiments show the viability of using the Gate-Shift technique to improve devices breakdown voltage to circa 29 V, while other electrical parameters are kept at reasonable values. From the availability of these high voltage NMOS transistors it can be concluded that designers can resort to last generation CMOS processes to develop cost smart power integrated circuits.