Xuan Guo, Danyu Wu, Lei Zhou, Huasen Liu, Jin Wu, Xinyu Liu
{"title":"A 4-GHz 32-bit direct digital frequency synthesizer in 0.25 µm SiGe HBT with SFDR > 46 dBc up to Nyquist bandwidth","authors":"Xuan Guo, Danyu Wu, Lei Zhou, Huasen Liu, Jin Wu, Xinyu Liu","doi":"10.1109/BCTM.2016.7738941","DOIUrl":null,"url":null,"abstract":"A 32-bit direct digital frequency synthesizer with a maximum operating frequency of 4.5 GHz fabricated in 0.25 μm SiGe HBT is presented. The phase-to-amplitude mapping circuit is implemented with nonlinear DAC coarse quantization and ROM-based piecewise linear interpolation. The measured SFDR is between 46 dBc and 60 dBc under a 4.0 GHz clock and the hopping time is less than 10 ns. This chip occupies 5.25 mm2 including bond pads and dissipates 3.46 W with a 4.0 V digital supply and 4.0V analog supply. The proposed DDFS demonstrates excellent performance achieving a FOM of 234.9 GHz · 2(SFDR/6)/W.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCTM.2016.7738941","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A 32-bit direct digital frequency synthesizer with a maximum operating frequency of 4.5 GHz fabricated in 0.25 μm SiGe HBT is presented. The phase-to-amplitude mapping circuit is implemented with nonlinear DAC coarse quantization and ROM-based piecewise linear interpolation. The measured SFDR is between 46 dBc and 60 dBc under a 4.0 GHz clock and the hopping time is less than 10 ns. This chip occupies 5.25 mm2 including bond pads and dissipates 3.46 W with a 4.0 V digital supply and 4.0V analog supply. The proposed DDFS demonstrates excellent performance achieving a FOM of 234.9 GHz · 2(SFDR/6)/W.