{"title":"VHDL design of embedded processor cores: the industry-standard microcontroller 8051 and 68HC11","authors":"M. Schutti, M. Pfaff, R. Hagelauer","doi":"10.1109/ASIC.1998.722990","DOIUrl":null,"url":null,"abstract":"Driven by the recent advances in VLSI technology, long-standing controller architectures have experienced a revival. The fast emerging IP (Intellectual Property) market is demanding embedded soft cores of well-established microcontrollers such as the 8051 and 68HC11. \"System on a chip\" technologies enable hardware designers to integrate their board designs, existing of several separate chips, into a single ASIC. For this transition a pool of adequate high level building blocks favorably implemented as technology-independent VHDL or Verilog descriptions is required.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1998.722990","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
Driven by the recent advances in VLSI technology, long-standing controller architectures have experienced a revival. The fast emerging IP (Intellectual Property) market is demanding embedded soft cores of well-established microcontrollers such as the 8051 and 68HC11. "System on a chip" technologies enable hardware designers to integrate their board designs, existing of several separate chips, into a single ASIC. For this transition a pool of adequate high level building blocks favorably implemented as technology-independent VHDL or Verilog descriptions is required.