Mapping Three Step Search algorithm onto a systolic array processor in H.264

Abstract

With the introduction of the H.264/AVC video coding standard, the compression efficiency and the flexibility has improved, compared to the previous coding standards. The computational expenses required for the motion estimation algorithm is very high, thereby making the algorithm very extensive. As a solution to this problem, we use the H.264/AVC standard to present the design criteria of mapping the Three Step Search (TSS) onto a systolic array processor.