A Hardware/Software Co-Design Approach for VLSI Circuit Partitioning

Abstract

The Fiduccia-Mattheyses (F-M) algorithm (1982) has proved to be an efficient algorithm for VLSI circuit partitioning, and it is widely used for several physical design automation applications. As digital circuits are becoming larger and more complex, methods such as the F-M algorithm are becoming slower and less efficient. To accelerate the F-M algorithm, an embedded computing system based on an FPGA chip is proposed. A speedup hardware module handles the computationally intensive functions while an embedded processor (a MicroBlaze soft-core) handles intense memory access operations that cannot be implemented efficiently with dedicated hardware. The co-design system can produce as good results as a pure software implementation, and can achieve better results than a pure-hardware based system by an average of 25%. The co-design based approach achieves results that are 2times faster than the pure-software based design