An array-based circuit for characterizing latent Plasma-Induced Damage

Abstract

An array-based Plasma-Induced Damage (PID) characterization circuit with various antenna structures is proposed for efficient collection of massive PID breakdown statistics. The proposed circuit reduces the stress time and test area by a factor proportional to the number of Devices Under Test (DUTs). Measured Weibull statistics from a 12-24 array implemented in 65nm show that DUTs with plate type antennas have a shorter lifetime compared to their fork type counterparts suggesting greater PID effect during the plasma ashing process.