Efficient layout style of CMOS output buffer to improve driving capability of low-voltage submicron CMOS IC's

Abstract

A novel square-type layout style is proposed to efficiently implement CMOS output buffer with larger W/L ratio into a smaller silicon layout area than that of conventional finger-type layout style. Using this proposed layout style, the driving capability of CMOS output buffer in low-voltage submicron CMOS IC's can be effectively improved without increasing the layout area.