A Hardware and Thermal Analysis of DVFS in a Multi-core System with Hybrid WNoC Architecture

Abstract

Evolution of CMOS manufacturing technologies has led to billions of transistors per chip, many core and System-on-Chip (SoC) realizations in current day systems. But maintaining this trend is a significant challenge due to the power and thermal issues. As the devices are scaled and number of transistors on the chip increases, the power density across the chip increases rapidly with each generation. This further results in increased system temperature that can cause damage to the system. Dynamic Voltage/Frequency Scaling (DVFS) schemes reduce the power consumption without significant loss in system performance. In this paper, we design and evaluate a centralized DVFS control mechanism for multi core systems and discuss its merits and overheads. One of the major issues with centralized controller implementation is the long delays associated with signal transmission between the controller and different clusters in the system. To alleviate this issue, we use wireless interfaces for transmitting controller signals along with the data signals. Towards this goal, we design a dual band transceiver & antenna for the wireless interfaces and present their implementation details. Finally the thermal profile of the proposed DVFS mechanism is analyzed and compared with normal operating conditions.