Power delivery for high performance microprocessors

Abstract

Summary form only given. Robust power delivery is considered one the prime challenges in chip design today. As the frequency and complexity of microprocessors increase, the static and dynamic components of power supply noise increase. However, keeping with Moore's law, the voltage supply to semiconductor chips have been scaling down, thereby reducing margins. There are other challenges including efficiency and power dissipation of the power delivery sub system itself. This presentation will try to discuss these challenges and the solutions employed by the industry to over come of these. The talk will conclude with some discussion on future technologies to improve the overall efficiency of power delivery.