A Test Generation Method Based on k-Cycle Testing for Finite State Machines

Abstract

Scan testing requires long test application time and a large hardware overhead. To avoid these disadvantages, design-for-testability methods at register transfer level based on non-scan testing are important. We assume that controllers and data paths in register transfer level circuits are isolated from each other at testing. We focus on test generation for controllers which are represented by finite state machines. In this paper, we propose a time expansion model with initial state constraints for controllers and its test generation method. Our proposed test generation method also uses the information of finite state machines. Experimental results show that our proposed method achieved higher fault coverage by 8.9% on average for all controllers compared with a commercial tool whose test generation algorithms use a time expansion model.