{"title":"A stable programming pulse generator for high-speed programming single power supply voltage flash memories","authors":"T. Tanzawa, T. Tanaka","doi":"10.1109/VLSIC.1995.520691","DOIUrl":null,"url":null,"abstract":"This paper describes a stable programming pulse generator to reduce not only the pumping-up time under a low power supply voltage condition, but also the power consumption under a high power supply voltage condition. Moreover, the fluctuation of the programming pulse width is controlled within /spl plusmn/0.5% under the condition of a power supply voltage fluctuation of /spl plusmn/20%. As a result, the increase of the programming pulse width under the low voltage condition is eliminated, and the total programming time can be reduced by about 30%. Furthermore, the proposed 10/spl mu/s delay circuit area can be reduced to 42% of the conventional one.","PeriodicalId":256846,"journal":{"name":"Digest of Technical Papers., Symposium on VLSI Circuits.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers., Symposium on VLSI Circuits.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1995.520691","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper describes a stable programming pulse generator to reduce not only the pumping-up time under a low power supply voltage condition, but also the power consumption under a high power supply voltage condition. Moreover, the fluctuation of the programming pulse width is controlled within /spl plusmn/0.5% under the condition of a power supply voltage fluctuation of /spl plusmn/20%. As a result, the increase of the programming pulse width under the low voltage condition is eliminated, and the total programming time can be reduced by about 30%. Furthermore, the proposed 10/spl mu/s delay circuit area can be reduced to 42% of the conventional one.