A SoC test strategy based on a non-scan DFT method

Abstract

This paper proposes a system-on-a-chip (SoC) test strategy based on a non-scan DFT method. Especially, we evaluate a basic DFT method, called NS-DFT, comparing it with a full scan DFT method. The experimental results for practical circuits and benchmark circuits demonstrate the efficiency of the NS-DFT.