Scalable Package-level RFI Filter for Digital Clock Noise Mitigation in 5-GHz and future 6-GHz WiFi Applications

Abstract

Digital clock frequency greater than 5-GHz is demanded due to fast signal processing for computer platforms. System-on-chip (SoC) and WiFi radio co-existence risk becomes increasing and has to be mitigated to support increasing data throughput requirement. Scalable package RFI filter solutions are studied for 5-GHz and future 6-GHz WiFi applications in the paper. Conventional RFI mitigation solutions have been investigated in package and board levels by on-board shielding and decoupling filter strategies. However, the solutions depend on PCB designs and RF component characteristics. Scalability and effectiveness of the solutions are therefore limited. In this study, an inductive meander structure is implemented at ground pad of the RF capacitor and allows tailoring effective filter frequency, which improves scalability of the package RFI filter solution. In addition, integrated package LC filter is designed with meander inductors and comb capacitor and shows effective filter frequency of 6.72 GHz and GHz-noise reduction of about 8 dB. This work provides effective and scalable gigahertz on-die clock noise mitigation solutions for WiFi applications.