Testing Crosstalk Faults of Data and Address Buses in Embedded RAMs

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2007-04-25 DOI:10.1109/VDAT.2007.373218

Jiunn-Der Yu, Jin-Fu Li, Tsu-Wei Tseng

引用次数: 1

Abstract

Random access memories (RAMs) have many long parallel wires which incur a greater probability for excessive crosstalk coupling effect. This paper presents a test algorithm for detecting crosstalk faults of address and data buses in RAMs. The test algorithm requires 12n+2m+2 Read/Write operations to cover 100% crosstalk faults for a RAM with m-bit addresses, n-bit data inputs/outputs. A BIST supporting March-CW and the proposed test is also implemented. Experimental results show that the area cost of the BIST is only about 3.1% for an 8 Ktimes16-bit RAM based on TSMC 0.18 mum standard cell library.

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嵌入式ram中数据和地址总线串扰故障的测试

随机存储器(ram)具有许多长的平行导线，这使得其产生过多串扰耦合效应的可能性较大。提出了一种检测ram中地址和数据总线串扰故障的测试算法。对于m位地址、n位数据输入/输出的RAM，测试算法需要12n+2m+2个读/写操作来覆盖100%的串扰故障。同时还实现了一个支持March-CW和提议测试的BIST。实验结果表明，基于台积电0.18 mum标准单元库的8 ktimes 16位RAM的面积成本仅为3.1%左右。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

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