RF LDMOS characterization and its compact modeling

Abstract

This paper presents characterization of power LDMOS using device simulation and analytical modeling. Features of the LDMOS such as graded channel and quasi-saturation effect which result in a peculiar behavior on capacitance and nonlinear LDD resistance are analyzed and modeled using device simulation. A compact model for LDMOS is implemented in HSPICE based on additional lumped elements, combined with the BSIM3 MOSFET model.