Prediction of the degradation of a hetero-junction bipolar transistor accompanied with aging simulation

Abstract

An empirical reliability model is proposed here that is able to predict parameter degradation for a SiGe Hetero-junction Bipolar Transistor (HBT) by scaling stress time laterally producing a universal curve that describes whole time evolution of degradation. The predictability of the degradation pattern is demonstrated in experiments at a forward active mode as well as the reverse Veb stress accounting for bias and current dependence of degradation. Furthermore, our model and methodology enables us to do an aging simulation at the circuit level.