Reduced complexity single core based HEVC video codec processor for mobile 4K-UHD applications

Abstract

A future video codec processor will have to adopt the newly standardized High Efficiency Video Coding (HEVC/H.265) in a short time due to the limit of H.264's coding efficiency for large sized UHD images. This paper combines our designed decoder and encoder for HEVC and proposes a low complexity HEVC video codec processor. We developed this codec processor with Samsung 28nm CMOS process in this year and the size of this low complexity codec keeps within the bounds of that of a conventional H.264/AVC chip. This single core based processor has an optimal mode decision with a simplified Rate Distortion Optimization (RDO) and a low power Skip mode. The encoder's BD-rate loss is 35% compared with HM-13.0 and the power consumption is below 250mW when entering the Skip mode. The chip and its internal SRAM size are 7.3 × 7.5mm2 and 300kB each and the maximum frequency is 600MHz when 4K-UHD encoding mode at 30 fps.