Long retention time of embedded DRAM macro with thin gate oxide film transistors

Abstract

This paper describes the advantages of the thin gate oxide transistors with negative word-line (WL) architecture implemented in the embedded DRAM macro. The macros with the negative WL architecture are fabricated as well as the macros with the conventional WL architecture. We found the retention time of the negative WL architecture is longer by more than 5 times than that of the conventional WL architecture.