Modular Design and Implementation of FPGA-Based Tap-Selective Maximum-Likelihood Channel Estimator

Abstract

The modular design of the optimal tap-selective maximum-likelihood (TS-ML) channel estimator based on field- programmable gate array (FPGA) technology is studied. A novel range reduction algorithm is included in the natural logarithmic function (NLF) emulator based on the coordinate rotation digital computer (CORDIC) methodology and is integrated into the TS- L channel estimator system. The low-complexity TSML algorithm, which is employed for sparse multipath channel estimation, is proposed for long-range broadband block transmission systems. Furthermore, the proposed range reduction algorithm aims to solve the limited interval problem in the CORDIC algorithm. The modular approach facilitates the reuse of modules.