PLA test pattern generation with orthogonal transform

Abstract

It is known that test pattern generation even for fixed structured realizations of digital circuits, i.e. PLAs is a NP-complete problem. With respect to the growing complexity of integrated circuits, this process has to be optimized to avoid large development and production cycles. The target of the authors' work is a method (as a part of fault simulation), which speeds up the process of test pattern generation for regular structures as PLAs, ROMs, RAMs and which also reduces time and storage complexity.<>