Implementation of Checkers for DFT Gaskets using SV/UVM

Abstract

DFT (Design for Testability) is an important additional logic that is inserted in an ASIC across the functional logic to aid post-production testing of the chip and to evaluate the faults in silicon that could have caused due to imperfections in fabrication process. DFT gasket verification is required because DFT is again implemented by Engineers which is prone to human errors. In today's ever-growing complexity of Systems-on-Chip (SoC)s, insufficient or inefficient DFT support due to poor specification, implementation or lax design procedures can suddenly become essential to meet market deadlines and delivering products under budget and tight schedules. The goal of this project is to provide a comprehensive, systematic, and completely automated approach for verification of DFT gaskets. The gaskets have to work predictably being cycle-accurate and in sequence as per expectation. Any deviation from the specification could have serious consequences including chip failure, subsequently causing billions of $ cost. An adoptable, random, predictable, cycle-accurate and robust infrastructure had to be built to verify the DFT gaskets so as to ensure the design is bug free. To be reusable, we have chosen UVM as methodology for environment and SystemVerilog as language for verification. Developing the scenarios in testcases and subsequently checkers for the same was carried out. Here DFT gaskets are On-chip clock controller and SRAM. Working of checkers is to compare the actual data expected data. Exceed application was used for connecting to server, Synopsys VCS was used for simulation and Synopsys Verdi tool for debugging.