A study on power and delay reduction techniques of latched comparator

Abstract

Comparators play the role of brain in any conversion system as the precision of any Analog to digital converter solely depends upon the performance metrics of comparator Thus it is important to optimize the trade-off between two main parameters, one is speed and other is power consumption. Together with power consumption, a comparator's design must consider several performance metrics, including input-referred offset voltage, delay, voltage gain, supply voltage, kickback noise and common-mode voltage level. A combination of low power with less delay in dynamic comparators is demanded for efficient analog to digital converters. This work focuses on contrasting and analyzing various research works that have been reported on power and delay optimization. Also, modified shared charge reset technique where we have sustained preamplifier gain until comparison phase. Also, power is optimized fixed value for a wider range of common mode voltage.