A practical method for digitally calibrating gain error of integrated ADCs

2014 IEEE Workshop on Electronics, Computer and Applications Pub Date : 2014-05-08 DOI:10.1109/IWECA.2014.6845545

Rongbin Hu, Yu Wen, Xiaoying Zhang

引用次数: 0

Abstract

A kind of practical method for digitally gain calibration of ADCs is proposed. The method is given in details as well as the architecture and circuit. The method has been successfully applied on a two-channel 8-bit time-interleaved ADC. Simulation shows that the gain of the 8-bit ADC can be adjusted with a step of 0.012dB and a full scale range of about 3dB. The measurement shows that the 8-bit ADC has a SNR of 37dB and 45dB before and after calibration, respectively.

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一种数字式校正集成adc增益误差的实用方法

提出了一种实用的adc数字增益校准方法。详细介绍了该方法，并给出了结构和电路。该方法已成功应用于一个双通道8位时间交错ADC上。仿真结果表明，该8位ADC的增益可调步长为0.012dB，满量程约为3dB。测量结果表明，该8位ADC在校准前后的信噪比分别为37dB和45dB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2014 IEEE Workshop on Electronics, Computer and Applications

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