Optimization of Annealing Process Conditions to Reduce Gate Induced Drain Leakage Current in Buried-Gate FETs

Abstract

As devices shrink, mitigating off-state power consumption has become a major concern for dynamic random access memory (DRAM) product development. The interface trap induced reduction of the retention time of DRAM cells has become increasingly critical due to aggressive device shrinkage. In this paper, the influence of reliability evaluation after device manufacturing on the number of interface traps in buried-channel-array-transistors and the optimal H2 annealing temperature were investigated for the reduction of trap-induced leakage currents that cause retention time degradation in DRAM cells. This study is expected to solve the problem of retention time and off-state power consumption caused by interface traps and to be utilized as a cornerstone for next-generation DRAM development.