A bit-serial VLSI receptive field accumulator

Abstract

A digital bit-serial VLSI chip for accumulating neural activations of a population of neurons that form a linear receptive field is discussed. This type of VLSI circuit is complementary to the best-match classifiers described in the literature. The circuit is called a brute force detector (BFD). The authors have designed and fabricated a prototype BFD neuron cascade through MOSIS in a 3-μm p-well CMOS process (M83M run). The results indicate that a wafer-scale, restructurable version of a detector could be constructed that could implement on the order of 105 receptive fields. A receiver using a cascade of such wafers would be of great practical value for radar and sonar applications as well as useful for the search for extraterrestrial intelligence (SETI)