E. Castillo, L. Parrilla, A. García, U. Meyer-Baese, A. Lloris
{"title":"Intellectual Property Protection of IP Cores at HDL Design Level with Automatic Signature Spreading","authors":"E. Castillo, L. Parrilla, A. García, U. Meyer-Baese, A. Lloris","doi":"10.1109/ENICS.2008.29","DOIUrl":null,"url":null,"abstract":"Watermarking techniques for Intellectual Property Protection (IPP) of IP cores at the HDL design level are proposed in this paper. The basic idea relies on spreading the bits of a digital signature at the HDL design level using combinational logic or look-up structures included within the original system. The techniques also include a secure and non-destructive signature extraction process. Furthermore, in this work the applicability has been extended due to the development of an automated tool for signature spreading purposes. Advances in the automated tool have been achieved by including new search algorithms, as the Simulated Annealing algorithm that achieves additional resources optimization while maintains reduced computation times. A detailed study of the research algorithms is carried out in order to show the advantages in terms of design effort, additional resources and execution times.","PeriodicalId":162793,"journal":{"name":"2008 International Conference on Advances in Electronics and Micro-electronics","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International Conference on Advances in Electronics and Micro-electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ENICS.2008.29","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Watermarking techniques for Intellectual Property Protection (IPP) of IP cores at the HDL design level are proposed in this paper. The basic idea relies on spreading the bits of a digital signature at the HDL design level using combinational logic or look-up structures included within the original system. The techniques also include a secure and non-destructive signature extraction process. Furthermore, in this work the applicability has been extended due to the development of an automated tool for signature spreading purposes. Advances in the automated tool have been achieved by including new search algorithms, as the Simulated Annealing algorithm that achieves additional resources optimization while maintains reduced computation times. A detailed study of the research algorithms is carried out in order to show the advantages in terms of design effort, additional resources and execution times.