(Invited) ESD-RFIC Co-design methodology

Abstract

RF ESD protection circuitry design emerges as a big challenge to RF IC design, where the main problem is associated with performance degradation of RF IC due to ESD-induced parasitics. It has been difficult to incorporate the ESD impacts into RF IC design due to lack of proper co-design approach and ESD device models. This paper presents a new ESD-RFIC co-design methodology, including RF ESD design optimization and characterization, as well as RF I/O re-matching techniques, developed to enable wholechip design optimization of ESD-protected RF IC circuits, which is verified by practical designs in 0.18 mum RFCMOS.