Bursty jitter in high-speed I/O due to power-state transition and its impact on signal integrity

Abstract

Accurately predicting power supply noise (PSN) induced jitter is crucial to link signal integrity analysis. PSN induced jitter becomes more severe with a decreased supply level, or increased design density. It exhibits strong time dependence due to power management technique employed in low-power design. For the first time, the bursty nature of PSN-induced jitter during power-state transition is accurately accounted for in full-link signal-integrity analysis. We present that power state transition frequency has a major impact on I/O link total jitter. This phenomenon that will be demonstrated with jitter simulations can be utilized to prevent over-design provided architecture-level wake-up behavior is determined.