Threshold voltage instability in organic TFT with SiO2 and SiO2/parylene-stack dielectrics

Abstract

We study the charge trapping/detrapping kinetics on pentacene-based organic thin-film-transistors featuring SiO2 and SiO2/parylene C stack gate insulators. The threshold voltage variation is correlated with the gate pulse width and amplitude, and it is due to charge trapping, rather than permanent degradation. The detrapping kinetics is thermally-activated and it is accelerated if the device is illuminated. The additional parylene layer brings benefits by strongly reducing the charge trapping/detrapping, and increasing the hole mobility and the drain current.