A 1V 10-bit 500KS/s energy-efficient SAR ADC using Master-Slave DAC technique in 180nm CMOS

Abstract

This work verifies the technique - Master-Slave digital to analog converter (M-S DAC) - for reducing the significant energy dissipation of 93% in comparison with the conventional capacitor array in successive approximation register analog to digital converter (SAR ADC). This technique avoiding the redundant charge and discharge in larger capacitors is demonstrated by a fabricated chip in 180nm CMOS standard process, and reaches performance including signal-to-noise-and-distortion ratio of 59.2dB in equivalent 9.6-bit, power consumption of 28 μW at the sampling frequency of 500KS/s with the conditions of supplying voltage of 1V in core area of 0.15mm2.