Yield Improvement Methodology with addressing Design Systematics during Production Ramp-up

Jianhua Yin, Ian Chen, Rakesh Chokanathan, Suraj Gyawali, Yupei Du, Yuansong Wang, Xue Mei Liu, CT Lim, Wen Zhi Gao
{"title":"Yield Improvement Methodology with addressing Design Systematics during Production Ramp-up","authors":"Jianhua Yin, Ian Chen, Rakesh Chokanathan, Suraj Gyawali, Yupei Du, Yuansong Wang, Xue Mei Liu, CT Lim, Wen Zhi Gao","doi":"10.1109/asmc54647.2022.9792517","DOIUrl":null,"url":null,"abstract":"Fast product yield learning rate is very critical to shorten the design to market cycle time, especially for mobile products with only 2~3-year product lifetime. Based on the typical yield learning curve as a function of a product’ life cycle, systematic defects resulting from the interaction between design and process may dominate product yield loss. Root cause identification and technical solutions of these systematics are very critical to achieve a significant improvement in the stage of production ramp-up stage. In this paper, a yield improvement methodology is presented to address design systematics and has been successfully deployed in multiple cases during volume ramp-up production in 14nm and beyond technology.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/asmc54647.2022.9792517","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

Fast product yield learning rate is very critical to shorten the design to market cycle time, especially for mobile products with only 2~3-year product lifetime. Based on the typical yield learning curve as a function of a product’ life cycle, systematic defects resulting from the interaction between design and process may dominate product yield loss. Root cause identification and technical solutions of these systematics are very critical to achieve a significant improvement in the stage of production ramp-up stage. In this paper, a yield improvement methodology is presented to address design systematics and has been successfully deployed in multiple cases during volume ramp-up production in 14nm and beyond technology.
在产量提升过程中解决设计系统问题的良率改进方法
快速的产品良率学习率对于缩短从设计到市场的周期至关重要,特别是对于产品寿命只有2~3年的移动产品。基于典型的良率学习曲线作为产品生命周期的函数,由于设计和工艺之间的相互作用而产生的系统性缺陷可能主导产品良率损失。这些系统的根本原因识别和技术解决方案对于实现增产阶段的显著改善至关重要。在本文中,提出了一种良率改进方法,以解决设计系统问题,并已成功应用于14nm及以上技术量产过程中的多个案例。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信