Jianhua Yin, Ian Chen, Rakesh Chokanathan, Suraj Gyawali, Yupei Du, Yuansong Wang, Xue Mei Liu, CT Lim, Wen Zhi Gao
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引用次数: 0
Abstract
Fast product yield learning rate is very critical to shorten the design to market cycle time, especially for mobile products with only 2~3-year product lifetime. Based on the typical yield learning curve as a function of a product’ life cycle, systematic defects resulting from the interaction between design and process may dominate product yield loss. Root cause identification and technical solutions of these systematics are very critical to achieve a significant improvement in the stage of production ramp-up stage. In this paper, a yield improvement methodology is presented to address design systematics and has been successfully deployed in multiple cases during volume ramp-up production in 14nm and beyond technology.