Speeding-up polynomial multiplication on Virtex FPGAs: Finding the best addition method

Abstract

This paper presents a comparison between three addition methods for the implementation of a Serial/Parallel Polynomial Multiplier. Each one of the chosen methods has its own strong points, depending on the number of digits taken into account per cycle. The LUT6 on Virtex-6 FPGA family has a major impact over the performance achieved and a change in the structure of a single addition cell might lead to impressive improvements. The architecture of the multiplier is presented together with the approach for each addition method. Finally, a comparison between the performances achieved in each implementation case is made, showing that the architecture mapped on the 6-LUT FPGA is the best for most of the cases.