Cobalt subtractive etch for advanced interconnects

A. Rogozhin, A. Miakonkikh, A. Tatarintsev, Ildar I. Amirov, Konstantin V. Rudenko
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引用次数: 1

Abstract

The modern IC process consists of a 13-layer metallization stack. Critical dimensions are 30-40 nm at the M0- M2 metal layers and due to barrier resistance and electromigration reasons, copper is not the perfect choice nowadays. There are two main alternatives to copper on M0-M2 layers: cobalt and ruthenium. Return to the subtractive scheme could be a powerful solution for future interconnects although the dry etching process of the metal is required for it. In this paper, different approaches to plasma etching of cobalt are studied. CO- and halogen-containing plasmas were considered. It seems that etching in CO-based plasma is inefficient. The rate was only 2 nm/min in a wide temperature range. The low-temperature (60°C) process of the cobalt etching in BCl3/Ar plasma was developed. The etching rate for the process was 50 nm/min. All of the considered processes are found to be aggressive toward the mask.
用于高级互连的钴减法蚀刻
现代集成电路工艺由13层金属化堆栈组成。在M0- M2金属层的关键尺寸为30- 40nm,由于屏障电阻和电迁移的原因,铜现在不是完美的选择。在M0-M2层上有两种主要的铜替代品:钴和钌。回到减法方案可能是未来互连的一个强大的解决方案,尽管它需要金属的干蚀刻过程。本文研究了等离子体刻蚀钴的不同方法。考虑了CO和卤素等离子体。在co基等离子体中蚀刻似乎是低效的。在较宽的温度范围内,速率仅为2 nm/min。研究了BCl3/Ar等离子体低温(60℃)刻蚀钴的工艺。该工艺的蚀刻速率为50 nm/min。所有考虑的过程都被发现对掩膜具有侵略性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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