Design of Three-Valued Logic D-Latch Using GNRFET

G. Ravikishore, N.M Nanditha, Venna Vijaya Sree Swarupa, S. Saravanan
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引用次数: 1

Abstract

MVL is the promising alternative to the binary logic. GNRFET is more suitable for Multi-Valued Logic Circuits because it reduces power leakage, energy consumption. MVL logic provides less complexity, high speed circuit, small chip area in digital circuits. The GNRFETs are considered to regulate the Vth. Threshold voltage Vth control in GNRFET is possible by varying the width and no. of Dimer lines (N). In Ternary logic family there are 3 types of inverters Standard Ternary Inverter, Negative Ternary Inverter, Positive Ternary Inverter. To design ternary D-Latch NTI, STI, NAND gates are used. A latch is an electronic device, which changes its output based on the applied input. Latches are the smallest building blocks of memory. In the VLSI technology area, power consumption of the circuit is very important. In this paper, the performance of Three-Valued Logic D-Latch using GNRFET in terms of power, delay are calculated. The simulation of GNRFET based three valued logic D-Latch is done using HSPICE 32nm technology tool. It is observed that power is 20.60uW and delay is 150.04 ns.
基于gnfet的三值逻辑d锁存器设计
MVL是二进制逻辑的一种很有前途的替代方案。GNRFET更适合于多值逻辑电路,因为它减少了漏电和能耗。MVL逻辑在数字电路中提供了复杂度低、电路速度快、芯片面积小的特点。gnrfet被认为调节Vth。gnfet的阈值电压Vth控制可以通过改变宽度和no来实现。在三元逻辑家族中,有三种类型的逆变器,标准三元逆变器,负三元逆变器,正三元逆变器。为了设计三元d锁存器NTI、STI、NAND门。锁存器是一种电子装置,它根据施加的输入改变其输出。闩锁是内存中最小的构件。在VLSI技术领域,电路的功耗是非常重要的。本文从功率、延时等方面计算了采用gnfet的三值逻辑d锁存器的性能。利用HSPICE 32nm技术工具对基于GNRFET的三值逻辑d锁存器进行了仿真。观察到功率为20.60uW,延迟为150.04 ns。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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