Exploring hard and soft networks-on-chip for FPGAs

Abstract

We present an FPGA architecture with Time Division Multiplexed (TDM) wiring with hard network routers and use this architecture to implement a circuit switched Network-on-Chip. We compare this network to exiting approaches: either hard or soft implementations of the network on an FPGA. TDM wiring allows us to address the problem of interfacing high-speed hard-routers with slower soft cores. The router area is reduced in favour of more flexible TDM wiring components. Our approach is more power and area efficient than soft networks and more flexible than hard networks.