The Influence of Defect Distribution Function Parameters on Test Patterns Generation

2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI:10.1109/MIXDES.2007.4286222

M. Rakowski, W. Pleskacz, P. Borkowski

引用次数: 1

Abstract

This paper describes the analysis of influence of yield loss model parameters on the test patterns generation. The probability of shorts between conducting paths as well as the estimations of yield loss are presented on the example gates from industrial standard cell library in 0.8 mum CMOS technology.

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缺陷分布函数参数对测试模式生成的影响

本文分析了产量损失模型参数对试验图生成的影响。以工业标准电池库中的栅极为例，给出了0.8 μ m CMOS技术中导通路径间短路的概率和产率损失的估计。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2007 14th International Conference on Mixed Design of Integrated Circuits and Systems

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