High-temperature characterization of a PD SOI CMOS process with LDMOS and lateral bipolar structures

Abstract

High-temperature characterization of a 0.8 /spl mu/m partially-depleted (PD) silicon-on-insulator (SOI) CMOS process is reported. The process is designed for mixed analog/digital/high-voltage applications. The measurements have been realized on n-MOSFETs, on lateral bipolar transistors and on LDMOS transistors and demonstrate the interest of the process under consideration.