Environmental Impact Evaluation Methodology for Emerging Silicon-Based Technologies

Abstract

Semiconductor technology evolves rapidly to enable continued improvements in performance and capability, and reductions in cost. We emphasize the need also for rapid EHS assessment of new technology alternatives. This effort provides a rapid methodology for evaluating new process options in the research phase, particularly to identify unit processes which may be of environmental concern compared to existing technologies. The use of novel materials should be estimated, in the context of both the fabrication facility and the local and global natural cycles. Unit processes of concern should be jointly optimized on the three axes of cost, performance, and environment. A case study examining 3D integration of ICs, with a focus on the handle wafer unit process steps, illustrates the proposed methodology