{"title":"Hybrid Memristor-CMOS Based Up-Down Counter Design","authors":"K. Alammari, A. Ahmadi, M. Ahmadi","doi":"10.1109/ICECS49266.2020.9294786","DOIUrl":null,"url":null,"abstract":"The newly discovered Memristor device is finding its way in today's circuit design. It is believed that processing and saving data in Memristors improve chip performance, and they might become an alternative solution for the CMOS technology. This work presents the implementation of 4-bit Up-Down counter utilizing the hybrid Memristor-CMOS platform. The simulation results have proven design and functionality of the Memristive counter. The proposed counter employs fewer numbers of transistors than conventional CMOS counter. Therefore, the proposal has a small layout area and shows a reasonable reduction in power consumption and delay. While other Up-Down counter which relies on the pure Memristive method “IMPLY” reported less area. However, our work overcomes the issues of delay and complexity produced by the lengthy operational steps associated with IMPLY based counter.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS49266.2020.9294786","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The newly discovered Memristor device is finding its way in today's circuit design. It is believed that processing and saving data in Memristors improve chip performance, and they might become an alternative solution for the CMOS technology. This work presents the implementation of 4-bit Up-Down counter utilizing the hybrid Memristor-CMOS platform. The simulation results have proven design and functionality of the Memristive counter. The proposed counter employs fewer numbers of transistors than conventional CMOS counter. Therefore, the proposal has a small layout area and shows a reasonable reduction in power consumption and delay. While other Up-Down counter which relies on the pure Memristive method “IMPLY” reported less area. However, our work overcomes the issues of delay and complexity produced by the lengthy operational steps associated with IMPLY based counter.