Hybrid Memristor-CMOS Based Up-Down Counter Design

K. Alammari, A. Ahmadi, M. Ahmadi
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引用次数: 2

Abstract

The newly discovered Memristor device is finding its way in today's circuit design. It is believed that processing and saving data in Memristors improve chip performance, and they might become an alternative solution for the CMOS technology. This work presents the implementation of 4-bit Up-Down counter utilizing the hybrid Memristor-CMOS platform. The simulation results have proven design and functionality of the Memristive counter. The proposed counter employs fewer numbers of transistors than conventional CMOS counter. Therefore, the proposal has a small layout area and shows a reasonable reduction in power consumption and delay. While other Up-Down counter which relies on the pure Memristive method “IMPLY” reported less area. However, our work overcomes the issues of delay and complexity produced by the lengthy operational steps associated with IMPLY based counter.
基于混合忆阻器- cmos的上下计数器设计
新发现的忆阻器器件在当今的电路设计中发挥着重要作用。人们认为,在忆阻器中处理和存储数据可以提高芯片性能,并且它们可能成为CMOS技术的替代解决方案。本工作提出了利用混合忆阻器- cmos平台实现4位上下计数器。仿真结果验证了忆阻计数器的设计和功能。所提出的计数器比传统的CMOS计数器使用更少的晶体管数量。因此,该方案具有较小的布局面积,并显示出合理的降低功耗和延迟。而其他依赖于纯记忆方法的上下计数器“暗示”报告的面积较小。然而,我们的工作克服了与基于暗示的计数器相关的冗长操作步骤所产生的延迟和复杂性问题。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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