{"title":"Precision level output devices - Session 9","authors":"D. Rich, R. Carley","doi":"10.1109/cicc.2004.1358765","DOIUrl":null,"url":null,"abstract":"The first half of the session centers on the design of mixed-signal ICs that convert analog signals to pulse width modulated signals for the purpose of building high-efficiency amplifiers. After the break, our attention turns to high-performance Nyquist rate digital-to-analog converters. These are compelling topics of timely relevance and practical interest. In this session, we have a confluence of some of the best work that attacks highly intriguing open issues on the subject. The session kicks off with a description of a uniformly-sampled class D amplifier implemented in a 90 nanometer digital CMOS process. The paper addresses the challenges of handling relatively high-voltage power supplies that are switched at the output of a chip implemented in a deep submicron process. The output signal is tri-level. Continuing with a similar theme, the second paper alternatively adopts a discrete-sampled class-D implementation. A period randomly selected by a pseudo random-number generator replaces the fured-clock period. An interesting implementation of a delta-sigma modulator, replacing the traditional configuration of the first two authors, is discussed in our next paper. A seventh-order single-loop single-bit modulator is used. The switching transistors are wedged inside the feedback loop, creating design challenges due to the complex impedance of the load. A delta-sigma structure is also at the heart of our fourth paper, though in this instance, the authors adopt an asynchronous approach in the absence of sampling operations. The circuit operates in the current domain. First-and second order modulator structures are compared. Shifting to an invited tutorial paper on the design of current-steering digital-to-analog converters, our guest speaker examines the role of this technique when improving the linearity and sampling rates of digital-to-analog converters. Calibration methods for the current sources, effects of finite-output resistance, suppression of data-dependent errors, and current-switching circuits will be covered. We conclude with a mismatched-shaping technique to improve matching of the data converter. While this method has been popularized in delta-sigma structures, our presenter offers a new twist on the theme, and considers its implementation in a Nyquist digital-to-analog converter. From this, new techniques for shaping the output spectrum of the clock signal are derived.","PeriodicalId":407909,"journal":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/cicc.2004.1358765","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The first half of the session centers on the design of mixed-signal ICs that convert analog signals to pulse width modulated signals for the purpose of building high-efficiency amplifiers. After the break, our attention turns to high-performance Nyquist rate digital-to-analog converters. These are compelling topics of timely relevance and practical interest. In this session, we have a confluence of some of the best work that attacks highly intriguing open issues on the subject. The session kicks off with a description of a uniformly-sampled class D amplifier implemented in a 90 nanometer digital CMOS process. The paper addresses the challenges of handling relatively high-voltage power supplies that are switched at the output of a chip implemented in a deep submicron process. The output signal is tri-level. Continuing with a similar theme, the second paper alternatively adopts a discrete-sampled class-D implementation. A period randomly selected by a pseudo random-number generator replaces the fured-clock period. An interesting implementation of a delta-sigma modulator, replacing the traditional configuration of the first two authors, is discussed in our next paper. A seventh-order single-loop single-bit modulator is used. The switching transistors are wedged inside the feedback loop, creating design challenges due to the complex impedance of the load. A delta-sigma structure is also at the heart of our fourth paper, though in this instance, the authors adopt an asynchronous approach in the absence of sampling operations. The circuit operates in the current domain. First-and second order modulator structures are compared. Shifting to an invited tutorial paper on the design of current-steering digital-to-analog converters, our guest speaker examines the role of this technique when improving the linearity and sampling rates of digital-to-analog converters. Calibration methods for the current sources, effects of finite-output resistance, suppression of data-dependent errors, and current-switching circuits will be covered. We conclude with a mismatched-shaping technique to improve matching of the data converter. While this method has been popularized in delta-sigma structures, our presenter offers a new twist on the theme, and considers its implementation in a Nyquist digital-to-analog converter. From this, new techniques for shaping the output spectrum of the clock signal are derived.