Performance Comparision of Autocorrelation and CPRDIC Algorithm Implemented on FPGA for OFDM Based WLAN

Abstract

This paper deals with design and implementation of Autocorrelator and CORDIC algorithm for OFDM based WLAN on FPGA. The autocorrelator is used for frame detection and carrier frequency offset estimation. The CORDIC is used to estimate the frequency offset and to calculate the division in the channel estimation algorithm. A fast pipelined CORDIC architecture and autocorrelator is designed and implemented on FPGA. HDL and test bench is developed to simulate and verify the functionality of both the modules. The design is implemented on Spartan-2 100K, Spartan-3 100K and Virtex-2 2 Million gate capacity devices to check the performances of hardware implementation. It is found that as the technology changes from 130nm FPGA to 90nm FPGA the design speed increases from 100 MHz to 229 MHz for autocorrelator and 24 MHz to 55 MHz, at the same time the design consumes more power this is due to the fact that Virtex devices have more gate capacity and hence more power consumption. The sequential logic also reduces drastically. The design consumes almost equal number of macros on the entire implementation platform. The design is optimized for area and power requirements.