Automatic Hardware Design Tool Based on Reusing Transformation

Abstract

Automatic hardware design is currently drawing research attentions as it has the potential to free designers from low level manual design process. In this paper, we propose an automatic hardware design tool, which is able to automatically perform reusing transformation on circuits. With the number of available computation modules as input, the proposed hardware design tool automatically designs circuit and generates corresponding register transfer level (RTL) codes in term of Verilog HDL. Our FPGA implementation results show that this design tool can efficiently perform resource planning according to user specifications.