On-chip decoupling capacitor optimization technique

Sh. Melikyan Vazgen, H. S. Karo, V. Avetisyan, A. T. Hakhverdyan
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引用次数: 4

Abstract

On-chip decoupling capacitors used for reducing power supply noise. In this paper, a design technique for sizing and placing on-chip decoupling cells based on circuits switching activity is proposed. Evaluation of this methods on Universal Serial Bus Test Chip power and USB TC with new power structure indicates that the same approach of decoupling capacitors placement in different power structure can produce up to 30 percent improvement in power supply noise level.
片上去耦电容优化技术
片上去耦电容器,用于降低电源噪声。本文提出了一种基于电路开关活度的片上解耦单元尺寸和放置的设计方法。在通用串行总线测试芯片电源和具有新电源结构的USB TC上对该方法的评估表明,在不同电源结构中放置相同的去耦电容的方法可以使电源噪声水平提高30%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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