A high performance polysilicon TFT using RTA and plasma hydrogenation applicable to highly stable SRAMs of 16 Mbit and beyond

Abstract

A 0.4- mu m polysilicon TFT with I/sub on/ of 5 mu A and I/sub off/ of 10 fA developed by use of the LDO (lightly doped offset) structure and RTA (rapid thermal annealing) and plasma hydrogenation treatment is discussed. These technologies have proved to be essential in realizing high-performance deep submicron TFTs. Highly stable and low-power SRAMs of 16 Mb and beyond can be realized by employing these technologies. Models and mechanisms to explain the effects of various treatments on the performances of the TFTs are proposed.<>