{"title":"A 1 V 2.4/4.8 GHz 4.59 mW CMOS VCO with source degeneration based current mode logic flip-flops for direct conversion receivers","authors":"A. Perumal, A. Patra, T. K. Bhattacharyya","doi":"10.1109/TECHSYM.2011.5783845","DOIUrl":null,"url":null,"abstract":"A 1-V 2.4/4.8-GHz 4.59 mW Quadrature Voltage Controlled Oscillator (QVCO) has been designed in 0.18 µm CMOS technology. All-pMOS VCO followed by static frequency divider using source degeneration based D flip-flops is proposed. An accurate small signal analysis model of proposed D flip-flops is provided to estimate the maximum operating frequency of the divider. The advantages of proposed QVCO are analyzed in terms of phase noise and suppress the higher order (≥3) harmonics through linearization. The best overall performance is displayed by the inversion mode pMOS varactor. The proposed QVCO is tuned from 2.4 to 2.5 GHz with a tuning voltage varying from 0 to 1 V, additional 80 MHz increased by switched capacitor array (SCA). Compared to the conventional QVCO, the proposed QVCO shows good 1/ƒ3 close-in phase noise. The simulated results shows about 6.0 dB, 8.0 dB, 6.0 dB and 0 dB of phase noise improvement at 10 kHz, 100 kHz, 1 MHz and 3 MHz offset from a 2.4 GHz carrier frequency. The input sensitivity of the divider is simulated from 50 mV to 510 mV to achieve the operating frequency varies from 3.0 GHz to 6.2 GHz at 1-V supply.","PeriodicalId":193763,"journal":{"name":"IEEE Technology Students' Symposium","volume":"96 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Technology Students' Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TECHSYM.2011.5783845","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A 1-V 2.4/4.8-GHz 4.59 mW Quadrature Voltage Controlled Oscillator (QVCO) has been designed in 0.18 µm CMOS technology. All-pMOS VCO followed by static frequency divider using source degeneration based D flip-flops is proposed. An accurate small signal analysis model of proposed D flip-flops is provided to estimate the maximum operating frequency of the divider. The advantages of proposed QVCO are analyzed in terms of phase noise and suppress the higher order (≥3) harmonics through linearization. The best overall performance is displayed by the inversion mode pMOS varactor. The proposed QVCO is tuned from 2.4 to 2.5 GHz with a tuning voltage varying from 0 to 1 V, additional 80 MHz increased by switched capacitor array (SCA). Compared to the conventional QVCO, the proposed QVCO shows good 1/ƒ3 close-in phase noise. The simulated results shows about 6.0 dB, 8.0 dB, 6.0 dB and 0 dB of phase noise improvement at 10 kHz, 100 kHz, 1 MHz and 3 MHz offset from a 2.4 GHz carrier frequency. The input sensitivity of the divider is simulated from 50 mV to 510 mV to achieve the operating frequency varies from 3.0 GHz to 6.2 GHz at 1-V supply.