A negotiated congestion based router for simultaneous escape routing

2010 11th International Symposium on Quality Electronic Design (ISQED) Pub Date : 2010-03-22 DOI:10.1109/ISQED.2010.5450514

Q. Ma, Tan Yan, Martin D. F. Wong

{"title":"A negotiated congestion based router for simultaneous escape routing","authors":"Q. Ma, Tan Yan, Martin D. F. Wong","doi":"10.1109/ISQED.2010.5450514","DOIUrl":null,"url":null,"abstract":"The negotiated congestion based routing scheme finds success in FPGA routing and IC global routing. However, its application in simultaneous escape routing, a key problem in PCB design, has never been reported in previous literature. In this paper, we investigate how well the negotiated congestion based router performs on escape routing problems. We propose an underlying routing graph which correctly models the routing resources of the pin grids on board. We then build a Negotiated Congestion based Escape Router (NCER) by applying the negotiated congestion routing scheme on the constructed routing graph. We compare the performance of NCER with that of Cadence PCB router Allegro on 14 industrial test cases, and experimental results show that the two routers have comparable routability: each of them completely routes 7 test cases. Moreover, we observe that NCER and Allegro exhibit complementary behaviors: each is able to solve most of the test cases that the other cannot solve. Together, they completely route 11 test cases. Therefore, by using NCER as a supplement to Allegro, we can solve a broader range of escape routing problems.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"29","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 11th International Symposium on Quality Electronic Design (ISQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2010.5450514","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 29

Abstract

The negotiated congestion based routing scheme finds success in FPGA routing and IC global routing. However, its application in simultaneous escape routing, a key problem in PCB design, has never been reported in previous literature. In this paper, we investigate how well the negotiated congestion based router performs on escape routing problems. We propose an underlying routing graph which correctly models the routing resources of the pin grids on board. We then build a Negotiated Congestion based Escape Router (NCER) by applying the negotiated congestion routing scheme on the constructed routing graph. We compare the performance of NCER with that of Cadence PCB router Allegro on 14 industrial test cases, and experimental results show that the two routers have comparable routability: each of them completely routes 7 test cases. Moreover, we observe that NCER and Allegro exhibit complementary behaviors: each is able to solve most of the test cases that the other cannot solve. Together, they completely route 11 test cases. Therefore, by using NCER as a supplement to Allegro, we can solve a broader range of escape routing problems.

查看原文本刊更多论文

一种基于协商拥塞的路由器，用于同时逃逸路由

基于协商拥塞的路由方案在FPGA路由和IC全局路由中都取得了成功。然而，它在PCB设计中的关键问题——同步逃逸布线中的应用，在以往的文献中从未报道过。在本文中，我们研究了基于协商拥塞的路由器在逃逸路由问题上的表现。我们提出了一个底层路由图，它正确地模拟了板上引脚网格的路由资源。然后，通过在构造的路由图上应用协商拥塞路由方案，构建了一个基于协商拥塞的逃逸路由器(NCER)。我们将NCER与Cadence PCB路由器Allegro在14个工业用例上的性能进行了比较，实验结果表明，这两种路由器具有相当的可达性:每个路由器完全路由7个测试用例。此外，我们观察到NCER和Allegro表现出互补的行为:每个都能够解决另一个不能解决的大多数测试用例。它们一起完全路由了11个测试用例。因此，通过使用NCER作为Allegro的补充，我们可以解决更广泛的逃逸路由问题。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2010 11th International Symposium on Quality Electronic Design (ISQED)

自引率

0.00%

发文量