Pipelining computing stages in configurable multicore architectures

A. Azarian
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Abstract

Recently, there has been increasing interest on using task-level pipelining to accelerate the overall execution of applications mainly consisting of Producer-Consumer (P/C) tasks. In this PhD work we propose an approach to achieve pipelining execution of P/C pairs of tasks in FPGA-based multicore architectures. The current approach is able to speedup the overall execution of successive, data-dependent tasks, by using multiple cores and specific customization features provided by FPGAs. An important component of our approach is the use of customized inter-stage buffer schemes to communicate data and to synchronize the cores associated to the P/C tasks. To improve the performance, we propose a technique to optimize out-of-order communication between P/C pairs when the consumer requests more than once each data element produced, a behavior present in many applications (e.g., image processing). The current FPGA-based experimental results show the feasibility of our approach in both in-order and out-of-order P/C tasks. Moreover, the results using our approach to task-level pipelining and a multicore architecture reveal noticeable performance improvements for a number of benchmarks over a single core implementation without using task-level pipelining.
可配置多核体系结构中的流水线计算阶段
最近,人们对使用任务级流水线来加速主要由生产者-消费者(P/C)任务组成的应用程序的整体执行越来越感兴趣。在这项博士工作中,我们提出了一种在基于fpga的多核架构中实现P/C对任务的流水线执行的方法。目前的方法能够通过使用fpga提供的多核和特定的定制功能来加速连续的、依赖数据的任务的整体执行。我们方法的一个重要组成部分是使用定制的阶段间缓冲方案来通信数据并同步与P/C任务相关的核心。为了提高性能,我们提出了一种技术来优化P/C对之间的乱序通信,当消费者对产生的每个数据元素请求不止一次时,这种行为存在于许多应用程序中(例如,图像处理)。目前基于fpga的实验结果表明,我们的方法在有序和无序的P/C任务中都是可行的。此外,使用我们的任务级流水线和多核体系结构方法的结果显示,在不使用任务级流水线的情况下,与单核实现相比,许多基准测试的性能有了明显的提高。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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