{"title":"Pipelining computing stages in configurable multicore architectures","authors":"A. Azarian","doi":"10.1109/FPL.2013.6645611","DOIUrl":null,"url":null,"abstract":"Recently, there has been increasing interest on using task-level pipelining to accelerate the overall execution of applications mainly consisting of Producer-Consumer (P/C) tasks. In this PhD work we propose an approach to achieve pipelining execution of P/C pairs of tasks in FPGA-based multicore architectures. The current approach is able to speedup the overall execution of successive, data-dependent tasks, by using multiple cores and specific customization features provided by FPGAs. An important component of our approach is the use of customized inter-stage buffer schemes to communicate data and to synchronize the cores associated to the P/C tasks. To improve the performance, we propose a technique to optimize out-of-order communication between P/C pairs when the consumer requests more than once each data element produced, a behavior present in many applications (e.g., image processing). The current FPGA-based experimental results show the feasibility of our approach in both in-order and out-of-order P/C tasks. Moreover, the results using our approach to task-level pipelining and a multicore architecture reveal noticeable performance improvements for a number of benchmarks over a single core implementation without using task-level pipelining.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"91 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 23rd International Conference on Field programmable Logic and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FPL.2013.6645611","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Recently, there has been increasing interest on using task-level pipelining to accelerate the overall execution of applications mainly consisting of Producer-Consumer (P/C) tasks. In this PhD work we propose an approach to achieve pipelining execution of P/C pairs of tasks in FPGA-based multicore architectures. The current approach is able to speedup the overall execution of successive, data-dependent tasks, by using multiple cores and specific customization features provided by FPGAs. An important component of our approach is the use of customized inter-stage buffer schemes to communicate data and to synchronize the cores associated to the P/C tasks. To improve the performance, we propose a technique to optimize out-of-order communication between P/C pairs when the consumer requests more than once each data element produced, a behavior present in many applications (e.g., image processing). The current FPGA-based experimental results show the feasibility of our approach in both in-order and out-of-order P/C tasks. Moreover, the results using our approach to task-level pipelining and a multicore architecture reveal noticeable performance improvements for a number of benchmarks over a single core implementation without using task-level pipelining.