Comprehensive process design for low-cost chip packaging with circuit-under-pad (CUP) structure in porous-SiOCH film

Abstract

Chip packaging technology with a circuit-under-pad (CUP) structure is developed for porous SiOCH (k=2.55)/Cu dual-damascene interconnects. Wire bonding damage is mainly improved by the pad structure. For the molding process, it is important to decrease the coefficient of thermal expansion (CTE) of the molding compounds. Combining the stress controls in these packaging processes with the contrived low-k deposition, high performance 65 nm-node ULSI chips are furnished in low-cost QFP with conventional wire bonding.