Vertical III-V nanowire MOSFETs, TFETs, and CMOS-Gates on Si: Processing in 3D

Abstract

III-V MOSFETs are candidates for extension of the scaling roadmap beyond 10 nm. In the vertical direction, the requirements on gate-length scaling is less stringent and vertical III-V nanowire FETs are thus attractive for high density and low-power applications. While growth in the vertical direction allows flexibility in heterostructure combination and eases the path for integration on Si substrates, the processing in the vertical direction is still regarded challenging. Processing on the length scale of a few tens of nanometers has nevertheless been demonstrated including processing of vertical nanowire transistors with a diameter of 10 nm. Besides logic applications, III-V MOSFETs hold promises in the area of millimeter-wave electronics.